Field of the Invention
The present invention generally relates to a data transmission system in which data read out of a memory is transmitted to another memory, and more particularly to a data transmission system by which data transmission requests can be supplied to the data transmission system without consideration of bus/address boundary rules.
A DMA controller which is a type of data transmission system performs data transmission control between memories. When the DMA controller receives DMA information (an address of a transmission side memory, an address of a receiving side memory, the amount of data to be transmitted and a transmission unit), the DMA controller performs the data transmission control so that data read out of the transmission side memory is transmitted to the receiving side memory without interposition of a CPU. A bus connected to the DMA controller is applied with a bus/address boundary rule which indicates a data length capable of being accessed from an address.
Under the bus/address boundary rule applied to a bus, the data length accessed from an address in a data transmission operation through the bus is limited as follows.
For example, in a data transmission operation from an address "0", data having data lengths of 1 byte, 2 bytes, 4 bytes, 8 bytes and 16 bytes can be accessed. From an address "1", only data having a data length of 1 byte can be accessed and from an address "2", data having data lengths of 1 byte and 2 bytes can be accessed. In a data transmission operation from an address "3", only data having a data length of 1 byte can be accessed and from an address "4", data having data lengths of 1 byte, 2 bytes and 4 bytes can be accessed. Further, in a data transmission operation from an address "5", only data having a data length of 1 byte can be accessed and from an address "6", data having data lengths of 1 byte and 2 bytes can be accessed.
Thus, in the data transmission operation using the DMA system, a unit amount of data to be transmitted has to be selected in accordance with the address. The unit amount of data to be transmitted is referred to as a transmission unit.
However, it is difficult to select the transmission unit in accordance with the address from which data is accessed. Thus, in a conventional case, the transmission unit is limited to a minimum value (e.g., 1 byte) which can be accessed from all addresses.
On the other hand, when the transmission unit is not limited to the minimum value, addresses of the transmission side memory and the receiving side memory (and the amount of data to be transmitted which does not agree with the bus/address boundary rule for the bus) are inhibited in the data transmission control. In addition, it is required that the addresses of the transmission side memory and the receiving side memory and the amount of data to be transmitted have to agree with the bus/address boundary rule for the bus. As a result, the data transmission control is performed under a condition in which a relationship between a specified address and a specified transmission unit satisfies the bus/address boundary rule. In addition, the data transmission control is performed in a manner based on a difference between the bus/address boundary rules for buses for the transmission side memory and the receiving side memory.
However, in the case where the transmission unit is limited to the minimum value, the data transmission speed is decreased.
In the case where addresses of the transmission side memory, the receiving side memory, and the amount of data to be transmitted do not agree with the bus/address boundary rule for the bus, data transmission control is inhibited. Further, in the case where it is required that the addresses of the transmission side memory and the receiving side memory and the amount of data to be transmitted have to agree with the bus/address boundary rule for the bus, the request for the data transmission operation to the DMA system has to be performed in consideration of the bus/address boundary rule. In the latter case, a large amount of shifting operations have to be performed.